In this article, we will explore the fascinating world of ARM Cortex-X4, where we will take a look at its origins, evolution and significance in today's society. ARM Cortex-X4 has occupied a prominent place in human history, playing a fundamental role in various areas, from culture and science, to politics and economics. Over the years, ARM Cortex-X4 has been the subject of study, debate and controversy, sparking the interest of academics, experts and hobbyists alike. Through a detailed and exhaustive analysis, we will delve into the multiple facets of ARM Cortex-X4, discovering its influence and relevance in the contemporary world.
| General information | |
|---|---|
| Launched | 2023 |
| Designed by | ARM Ltd. |
| Performance | |
| Address width | 40-bit |
| Cache | |
| L1 cache | 128 KiB (64 KiB I-cache with parity, 64 KiB D-cache) per core |
| L2 cache | 512–2048 KiB per core |
| L3 cache | 512 KiB – 32 MiB (optional) |
| Architecture and classification | |
| Microarchitecture | ARM Cortex-X4 |
| Instruction set | ARMv9.2-A |
| Physical specifications | |
| Cores |
|
| Products, models, variants | |
| Product code name |
|
| Variant | |
| History | |
| Predecessor | ARM Cortex-X3 |
| Successor | ARM Cortex-X925 |
The ARM Cortex-X4 is a high-performance CPU core from Arm, released in 2023[1] as part of Arm's "total compute solution".[2] It serves as the successor of ARM Cortex-X3.[3]
X-series CPU cores generally focus on high performance, and can be grouped with other ARM cores, such as ARM Cortex-A720 or/and ARM Cortex-A520 in a System-on-Chip (SoC).[4][5]
The processor implements the following changes:[3][4][5]
Performance claims:
| uArch | Cortex-A78 | Cortex-X1 | Cortex-X2 | Cortex-X3 | Cortex-X4 | Cortex-X925 |
|---|---|---|---|---|---|---|
| Code name | Hercules | Hera | Matterhorn-ELP | Makalu-ELP | Hunter-ELP | Blackhawk |
| Architecture | ARMv8.2 | ARMv9 | ARMv9.2 | |||
| Peak clock speed | ~3.0 GHz | ~3.3 GHz | ~3.4 GHz | ~3.8 GHz | ||
| Decode width | 4 | 5 | 6 | 10[6] | ||
| Dispatch | 6/cycle | 8/cycle | 10/cycle | |||
| Max in-flight | 2x 160 | 2x 224 | 2x 288 | 2x 320 | 2x 384 | 2x 768 |
| L0 (Mops entries) | 1536[7] | 3072[7] | 1536 | 0[6] | ||
| L1-I + L1-D | 32+32 KiB | 64+64 KiB | ||||
| L2 | 128–512 KiB | 0.25–1 MiB | 0.5–2 MiB | 2–3 MiB | ||
| L3 | 0–8 MiB[8] | 0–16 MiB | 0–32 MiB | |||