Altera Hardware Description Language
In this article, we want to explore Altera Hardware Description Language and delve deeper into its different aspects and meanings. Altera Hardware Description Language is a topic that has captured the attention of many people today and has generated great interest in society. Throughout this article, we will analyze different approaches and points of view on Altera Hardware Description Language, as well as its importance in different contexts and areas of study. We will also examine its evolution over time and how it has impacted people's daily lives. In short, we will delve into the world of Altera Hardware Description Language to understand its relevance and influence on modern society.
 | This article needs additional citations for verification. (June 2023) |
Altera Hardware Description Language (AHDL) is a proprietary hardware description language (HDL) developed by Altera Corporation. AHDL is used for digital logic design entry for Altera's complex programmable logic devices (CPLDs) and field-programmable gate arrays (FPGAs). It is supported by Altera's MAX-PLUS and Quartus series of design software.[1] AHDL has an Ada-like syntax, while its feature set is comparable to the synthesizable portions of the Verilog and VHDL hardware description languages. In contrast to HDLs such as Verilog and VHDL, AHDL is a design-entry language only; all of its language constructs are synthesizable. By default, Altera software expects AHDL source files to have a .tdf extension (Text Design Files).
Example
% a simple AHDL up counter, released to public domain 13 November 2006 % % % % like c, ahdl functions must be prototyped % % PROTOTYPE: FUNCTION COUNTER (CLK) RETURNS (CNTOUT); % % function declaration, where inputs, outputs, and bidirectional pins are declared % % also like c, square brackets indicate an array % SUBDESIGN COUNTER ( CLK :INPUT; CNTOUT :OUTPUT; ) % variables can be anything from flip-flops (as in this case), tri-state buffers, state machines, to user defined functions % VARIABLE TIMER: DFF; % as with all hardware description languages, think of this less as an algorithm and more as wiring nodes together % BEGIN DEFAULTS TIMER.prn = VCC; % this takes care of d-ff resets % TIMER.clrn = VCC; END DEFAULTS; TIMER.d = TIMER.q + H"1"; END;
References
- ^ MAX+PLUS II AHDL (PDF) (6.0 ed.). San Jose, CA: Altera Corporation. November 1995. Retrieved 23 June 2023.
- Scarpino, Frank A., VHDL and AHDL Digital System Implementation. Prentice Hall PTR, 1998.
 | This electronics-related article is a stub. You can help Wikipedia by expanding it. |