Tu banner alternativo

ESi-RISC

Today, ESi-RISC is a topic that has become increasingly relevant in our society. It has become a point of interest for people of all ages and around the world. Its impact can be observed in different areas of daily life, from politics and economics, to culture and entertainment. ESi-RISC has sparked passionate debates and generated different opinions and perspectives. In this article, we will explore different aspects related to ESi-RISC, from its origin to its influence today, as well as the possible future scenarios that could arise as a result of its evolution.

Tu banner alternativo

eSi-RISC
DesignereSi-RISC
Bits16-bit/32-bit
Introduced2009
DesignRISC
TypeLoad–store
EncodingIntermixed 16 and 32-bit
BranchingCompare and branch and condition code
EndiannessBig or little
ExtensionsUser-defined instructions
Registers
8/16/32 General Purpose, 8/16/32 Vector

eSi-RISC is a configurable CPU architecture. It is available in five implementations: the eSi-1600, eSi-1650, eSi-3200, eSi-3250 and eSi-3264.[1] The eSi-1600 and eSi-1650 feature a 16-bit data-path, while the eSi-32x0s feature 32-bit data-paths, and the eSi-3264 features a mixed 32/64-bit datapath. Each of these processors is licensed as soft IP cores, suitable for integrating into both ASICs and FPGAs.[2]

Architecture

The main features of the eSi-RISC architecture are:[3]

eSi-3250 SoC architecture
  • RISC-like load/store architecture.
  • Configurable 16-bit, 32-bit or 32/64-bit data-path.
  • Instructions are encoded in either 16 or 32-bits.
  • 8, 16 or 32 general purpose registers, that are either 16 or 32-bits wide.
  • 0, 8, 16 or 32 vector registers, that are either 32 or 64-bits wide.
  • Up to 32 external, vectored, nested and prioritizable interrupts.
  • Configurable instruction set including support for integer, floating-point and fixed-point arithmetic.
  • SIMD operations.
  • Optional support for user-defined instructions, such as cryptographic acceleration .[4]
  • Optional caches (Configurable size and associativity).
  • Optional MMU supporting both memory protection and dynamic address translation.
  • AMBA AXI, AHB and APB bus interfaces.
  • Memory mapped I/O.
  • 5-stage pipeline.
  • Hardware JTAG debug.

While there are many different 16 or 32-bit Soft microprocessor IP cores available, eSi-RISC is the only architecture licensed as an IP core that has both 16 and 32-bit implementations.

Unlike in other RISC architectures supporting both 16 and 32-bit instructions, such as ARM/Thumb or MIPS/MIPS-16, 16 and 32-bit instructions in the eSi-RISC architecture can be freely intermixed, rather than having different modes where either all 16-bit instructions or all 32-bit instructions are executed. This improves code density without compromising performance. The 16-bit instructions support two register operands in the lower 16 registers, whereas the 32-bit instructions support three register operands and access to all 32 registers.

eSi-RISC includes support for Multiprocessing. Implementations have included up to seven eSi-3250's on a single chip.[5]

Toolchain

The eSi-RISC toolchain is based on combination of a port of the GNU toolchain and the Eclipse IDE.[6] This includes:

  • GCC – C/C++ compiler.
  • Binutils – Assembler, linker and binary utilities.
  • GDB – Debugger.
  • Eclipse – Integrated Development Environment.

The C library is Newlib and the C++ library is Libstdc++. Ported RTOSes include MicroC/OS-II, FreeRTOS, ERIKA Enterprise[7] and Phoenix-RTOS[8]

References

  1. ^ Electronics Weekly, 17 November 2009
  2. ^ [permanent dead link] EE Times, 17 November 2009
  3. ^ eSi-RISC eSi-3250 Technical Overview
  4. ^ Electronics Weekly, 2013
  5. ^ Design & Reuse, 2011
  6. ^ Archived 28 February 2012 at the Wayback Machine EnSilica, 2009
  7. ^ Electronics Weekly, 2010,
  8. ^ Cambridge Network 2013
Wikious
Boobota
Sagapedia