Willow Cove
In this article, we will explore and analyze different aspects related to Willow Cove. From its origin and history to its relevance today, through its impacts on society and its influence in different areas of daily life. Along these lines, we will delve in depth into Willow Cove to understand its importance and implications, as well as to reflect on its role in today's world. Through a detailed and exhaustive analysis, we will seek to shed light on this topic and offer an enriching perspective for the reader.
| General information | |
|---|---|
| Launched | September 12, 2020 |
| Designed by | Intel |
| Common manufacturer |
|
| Cache | |
| L1 cache | 80 KB per core: (32 KB instructions + 48 KB data) |
| Architecture and classification | |
| Technology node | Intel 10 nm SuperFin (10SF) |
| Instruction set | x86-64 |
| Extensions | |
| Products, models, variants | |
| Product code name | |
| History | |
| Predecessor | Sunny Cove |
| Successor | Golden Cove |
Willow Cove is a codename for a CPU microarchitecture developed by Intel and released in September 2020. Willow Cove is the successor to the Sunny Cove microarchitecture, and is fabricated using Intel's enhanced 10 nm process node called 10 nm SuperFin (10SF).[1] The microarchitecture powers 11th-generation Intel Core mobile processors (codenamed "Tiger Lake").[1][2]
The Willow Cove microarchitecture was succeeded by Golden Cove.[3]
Features
Intel first described Tiger Lake and Willow Cove during their Architecture Day in 2020.[4] Willow Cove is almost identical to the previous microarchitecture but introduces new security features, a redesigned cache subsystem, and higher clock speeds.[4] Intel claims that these changes, in addition to the new 10SF process node, give an additional 10–20% performance increase from Sunny Cove.[1]
Improvements
- Larger L2 caches (1.25 MB per core from 512 KB per core)
- Larger L3 caches (3 MB per core from 2 MB per core)
- A new AVX-512 instruction: Vector Pair Intersection to a Pair of Mask Registers, VP2INTERSECT[5][6]
- Control Flow Enforcement Technology to prevent return-oriented programming and jump-oriented programming exploitation techniques[7]
- Full memory (RAM) encryption[8]
- Indirect branch tracking and shadow stack
- Intel Key Locker[9][10]
- AVX/AVX2 instructions support for Pentium Gold and Celeron processors has been unlocked[6]
Products
Willow Cove powers Intel's 11th-generation Intel Core mobile processors (codenamed Tiger Lake). Tiger Lake-U processors were released on September 2, 2020,[11] while Tiger Lake-H35 were released on January 11, 2021.[12] Tiger Lake-H processors were launched on May 11, 2021.[13][14]
References
- ^ a b c Cutress, Dr Ian. "Intel's 11th Gen Core Tiger Lake SoC Detailed: SuperFin, Willow Cove and Xe-LP". www.anandtech.com. Archived from the original on November 24, 2020. Retrieved 2021-04-06.
- ^ "Intel teases its Ice Lake & Tiger Lake family, 10nm for 2018 and 2019". TweakTown. 2016-01-20. Retrieved 2021-02-15.
- ^ Cutress, Dr Ian. "Intel Alder Lake: Confirmed x86 Hybrid with Golden Cove and Gracemont for 2021". www.anandtech.com. Archived from the original on August 14, 2020. Retrieved 2021-02-15.
- ^ a b "Intel goes over Tiger Lake and Willow Cove at Architecture Day". Windows Central. 2020-08-13. Retrieved 2021-04-06.
- ^ "Compiler Support Getting Wired Up For AVX-512 VP2INTERSECT - Phoronix". www.phoronix.com. Retrieved 2020-01-14.
- ^ a b October 2020, Anton Shilov 16 (16 October 2020). "Intel's Latest Celeron and Pentium CPUs Finally Get AVX2, AVX-512 Support". Tom's Hardware. Retrieved 2020-10-19.
{{cite web}}: CS1 maint: numeric names: authors list (link) - ^ "A Technical Look at Intel's Control-flow Enforcement Technology". Intel. Retrieved 2020-09-02.
- ^ "Intel Releases New Technology Specification for Memory Encryption". Intel. Archived from the original on 2020-11-09. Retrieved 2020-09-02.
- ^ "Intel Key Locker Specification" (PDF). Retrieved 2023-10-11.
- ^ "Intel Key Locker Support Added to LLVM - Confirms Presence with Tiger Lake - Phoronix".
- ^ "2019 Intel Investor Meeting: The Transformation of the PC Sector" (PDF). 2019 Intel Investor Meeting. May 8, 2019. p. 11. Archived from the original (PDF) on 2019-10-29. Retrieved 2019-05-19.
- ^ Cutress, Dr Ian. "Intel's New H35 Series: Quad Core Tiger Lake now at 35 W for 5.0 GHz". www.anandtech.com. Archived from the original on January 11, 2021. Retrieved 2021-01-12.
- ^ Cutress, Dr Ian. "Intel Launches 11th Generation Core Tiger Lake-H: Eight Core 10nm Mobile Processors". www.anandtech.com. Archived from the original on May 11, 2021. Retrieved 2021-05-21.
- ^ Cutress, Dr Ian. "Intel's 8-Core Mobile Tiger Lake-H, at 45 W, to Ship in Q1". www.anandtech.com. Archived from the original on January 11, 2021. Retrieved 2021-01-12.